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| PI6C2972 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 Low Voltage PLL Clock Driver Features * Fully Integrated PLL * Output Frequency up to 125 MHz * Compatible with PowerPC and Pentium Microprocessors * 3.3V VCC * + 100ps Typical Cycle-to-Cycle Jitter * Packaging (Pb-free & Green available): - 52-pin LQFP (FC) Description The PI6C2972 are 3.3V compatible, PLL based clock driver devices targeted for high-performance CISC or RISC processor based systems. With output frequencies of up to 125 MHz and skews of 550ps the PI6C2972 are ideally suited for most synchronous systems. The devices offer twelve low skew outputs plus a feedback and sync output for added flexibility and ease of system implementation. The PI6C2972 features an extensive level of frequency programmability between the 12 outputs as well as the input vs output relationships. Using the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock edge prior to the coincident edges of the Qa and Qc outputs. The Sync output will indicate when the coincident rising edges of the above relationships will occur. The Power-On Reset ensures proper programming if the frequency select pins are set at power up. If the fselFB2 pin is held high, it may be necessary to apply a reset after power-up to ensure synchronization between the QFB output and the other outputs. The internal power-on reset is designed to provide this function, but with power-up conditions being dependent, it is difficult to guarantee. All other conditions of the fsel pins will automatically synchronize during PLL lock acquisition. The PI6C2972 offers a very flexible output enable/disable scheme. Note that all of the control inputs on the PI6C2972 have internal pull- up resistors. The PI6C2972 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive 50-ohm transmission lines. For series terminated lines each PI6C2972 output can drive two 50-ohm lines in parallel thus effectively doubling the fanout of the device. Pin Configuration fselFB0 Ext_FB GNDO GNDO VCCO VCCO GND0 VCCI QFB Qb0 Qb1 Qb2 Qb3 fselb1 fselb0 fsela1 fsela0 Qa3 VCCO Qa2 GNDO Qa1 VCCO Qa0 GND0 VCO_Sel 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 25 24 23 22 21 20 19 18 17 16 15 14 9 10 11 12 13 fselFB1 QSync GNDO Qc0 VCCO Qc1 fselc0 fselc1 Qc2 VCCO Qc3 GND0 Inv_Clk Frz_Clk Frz_Data fselFB2 GND1 PLL_EN Ref_Sel TClk_Sel TClk0 MR/OE TClk1 VCCA xtal1 xtal2 1 PS8590C 09/22/04 TCLK0 TCLK1 TCLK_Sel Ext_FB 0 1 PHASE DETECTOR VCO 1 V V /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 fsela0:1 fselb0:1 fselc0:1 fselFBO:1 2 2 2 2 Data Generator D Q Sync Frz /4, /6, /8, /10 Sync Pulse /2 0 1 D Q Sync Frz V V V V Output Disable Circuitry Frz_Data Inv_Clk 12 2 V 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2972 Low Voltage PLL Clock Driver Block Diagram xtal_1 xtal_2 VC0_Sel PLL_En REF_Sel D 0 Q Sync Frz Qa0 Qa1 Qa2 Qa3 LPF Sync Frz D Q Qb0 Qb1 Qb2 fselFB2 Qb3 MR/OE POWER-ON RESET D Q Sync Frz Qc0 Qc1 Qc2 Qc3 D Q QFB QSync Frz_Clk PS8590C 09/22/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2972 Low Voltage PLL Clock Driver Function Table 1 fs e la1 0 0 1 1 fs e la0 0 1 0 1 Qa /4 /6 /8 /12 fs e lb1 0 0 1 1 fs e lb0 0 1 0 1 Qb /4 /6 /8 / 10 fs e lc1 0 0 1 1 fs e lc0 0 1 0 1 Qc /2 /4 /6 /8 Function Table 2 fs e lFB2 0 0 0 0 1 1 1 1 fs e lFB1 0 0 1 1 0 0 1 1 fs e lFB0 0 1 0 1 0 1 0 1 QFB /4 /6 /8 /10 /8 / 12 / 16 / 20 Function Table 3 Control Pin VCO_Sel Ref_Sel TCLK_Sel PLL_En MR/OE Inv_CLK Logic '0' VCO/2 TCLK TCLK0 Bypass PLL Master Reset/Output Hi- Z Non- Inverted Qc2, Qc3 Logic '1' VCO Xtal TCLK1 Enable PLL Enable Outputs Inverted Qc2, Qc3 Crystal Recommendations Parame te rs Crystal Cut Resonance Freq. Tolernace Freq. Temp. Stability Operating Range Shunt Capacitance ESR Drive Level Aging Value Fundamental AT Cut Parallel Resonance 100ppm @ 25C 175ppm (0 to 70C) 0 to 70C < 7pF < 40- Ohm 5mW 5ppm / Year (First 3 years) 3 PS8590C 09/22/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 Timing Diagrams Qa( 12) Qa( 4) Qa( 6) Qa( 6) Qa( 8) Qc( 2) Qc( 6) Qc( 2) Qc( 8) Qc( 2) fVCO Sync Sync Sync Sync Sync Sync Sync Qa Qa Qc Qc 2:1 Mode 3:1 Mode 3:2 Mode 1:6 Mode 4:3 Mode 4:1 Mode 1:1 Mode 4 PI6C2972 Low Voltage PLL Clock Driver PS8590C 09/22/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2972 Low Voltage PLL Clock Driver Absolute Maximum Ratings Symbol VCC VI IIN TSTOR Parame te r Supply Voltage Input Voltage Input Current Storage Temperature -40 M in. -0.3 -0.3 M a x. 4.6 VDD +0.3 20 125 Units V V mA C *Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. DC Characteristics (TA = 0C to 70C, VCC = 3.3V 5%)(4) Symbol VIH VIL VOH VOL IIN ICC ICCA CIN C pd Per Output IOH = 20mA(2) IOL = 20mA(2) Note 3 Conditions Characte ris tic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Current Maximum Quiescent Supply Current Analog VCC Current Input Capacitance Power Dissipation Capacitance 25 190 15 2.4 0.5 120 215 20 4 pF mA M in. 2.0 Typ. M ax. 3.6 0.8 V Units Notes: 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. 2. The PI6C2972 outputs can drive series or parallel terminated 50 Ohm (or 50 Ohm to VCC/2) transmission lines on the incident edge. 3. Inputs have pull-up/pull-down resistors which affect input current. 4. Special thermal handling may be required in some configurations. 5 PS8590C 09/22/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2972 Low Voltage PLL Clock Driver PLL Input Reference Characteristic (TA = 0C to 70C) Symbol tr, tf fref frefDC txtal Note 5 Conditions Characte ris tics TCLK Input Rise/Falls Reference Input Frequency Reference Input Duty Cycle Crystal Oscillator Frequency Note 5 25 10 M in. M a x. 3.0 100, Note 5 75 25 Units ns MHz % MHz Notes: 5. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100 MHz, minimum input reference frequency is limited by the VCO lock range and the feedback divider. AC Characteristics (TA = 0C to 70C, VCC = 3.3V 5%) Symbol tr, tf tpw tpd tos fVCO Characte ris tics Output Rise/Fall Time (Note7) Output Duty Cycle (Note7) Propagation Delay Notes 7, 8, QFB = /8 Output- to- Output Skew VCO Lock Range Maximum Output Frequency Q (/2) Q (/4) Q (/6) Q (/8) Cycle-to-Cycle Jitter (Peak-to-Peak) Output Disable Time Output ENable TIme Maximum PLL Lock Time Maximum Frz_Clk Frequency 2 2 TCLK0 TCLK1 Note 7 200 Conditions 0.8 to 2.0V M in. 0 . 15 tCYCLE/2 -750 -270 -330 tCYCLE/2 500 13 0 70 Typ. M ax. 1.2 tCYCLE/2 +750 530 470 550 480 125 120 80 60 10 0 8 ns 10 10 20 ms MHz MHz ps Units ns fmax Note 7 tjitter tPLZ, tPHZ tPZL,tPZH tlock fMAX ps Notes: 7. 50 Ohm transmission line terminated into VCC/2 8. tpd is specified for a 50 MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/ longer input reference periods. The tpd does not include jitter. 6 PS8590C 09/22/04 0.25 mm 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2972 Low Voltage PLL Clock Driver Start Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0-D3 are the control bits for Qa0-Qa3, respectively D4-D7 are the control bits for Qb0-Qb3, respectively D8-D10 are the control bits for Qc1-Qc3, respectively D11 is the control bit for QSync Freeze Data Input Protocol Packaging Mechanical: 52-Pin LQFP (FC) 12.00 BSC .472 Square Square 10.00 BSC .394 0.09 0.20 .004 .008 GAUGE PLANE 0 7 0.45 .018 0.75 .030 1.60 Max. .063 .004 0.10 Seating Plane 1.00 REF .039 0.22 .009 0.38 .015 0.65 BSC .026 0.05 0.15 .002 .006 1.35 1.45 .053 .057 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Ordering Code PI6C2972FC PI6C2972FCE Package Code FC FC Package Type 52-pin LQFP Pb-free & Green, 52-pin LQFP Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 7 PS8590C 09/22/04 |
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